The present invention relates to the method of making semiconductor device, and more specifically relates to method of forming alignment mark used for exposure instrument and method of forming measurement mark for measuring relative error caused in exposure alignment.
Conventionally, in the method of making semiconductor device, method of forming the alignment mark and aligning is such that, after forming a film over the semiconductor substrate, a part of circuit pattern is formed on the film through the process of photolithography and etching, and concurrently the alignment mark is formed on a margin portion of the circuit pattern. Then, after forming a next film for new processing step over the entire surface of semiconductor substrate and coating photoresist, exposure is carried out by using the exposure instrument. In the conventional technology, preferrably alignment mark for use in each processing step is provisionally formed by a particular film pattern which has the smallest design margin between circuit patterns and which is needed the highest accuracy of relative positioning. Accordingly, alignment mark formed by the particular film pattern may be used mutually in the subsequent processing steps. Further, since the most general alignment method utilizes reflecting light or refracting light from the alignment mark without regard to the exposure methods of X-ray, electron beam and infrared light, the alignment mark is preferrably formed of opaque film such as polysilicon, metal silicide and aluminium used as electrode material and lead pattern material or comprised of steps on the semiconductor substrate, rather than a film having a very high transmitivity for alignment light, such as Si0.sub.2 (silicon dioxide) and PSG (phosphorus siligate glass).
FIG. 5 shows an example of such conventional manufacturing method. In the step of forming gate electrode material on a semiconductor substrate 31, an alignment mark 32 is concurrently formed (FIG. 5 (a)). Next, insulating layer film is formed in the form of PSG film (phosphorus siligate glass) 33 and transparent Si0.sub.2 (silicon dioxide) film 34 (FIG. 5 (b)). In order to carry out subsequent patterning on the gate electrode, a processing step is needed to remove a part of this insulating inter-layer film positioned above the gate electrode. Such processing step is generally called contact step. Such contact hole must be precisely formed without positional deviation with respect to the gate electrode. Accordingly, in order to eliminate alignment error due to indirect factors, the positioning is carried out by using the alignment mark 32 provisionally formed from the gate electrode material. After the contact step, in order to carry out the next lead patterning step, lead pattern material 36 is disposed on the semiconductor substrate and thereafter photoresist 35 is coated so as to carry out exposure. In this case, in view of the design margin, since the lead patterning should be carried out in precise positional relation to the contact hole, an alignment mark should be preferrably formed of the insulating inter-layer film. However, it is optically transparent material, and therefore actually the mark made of gate electrode material (opaque film) having relatively strict design margin is substitutionally used in place thereof (FIG. 5 (c)).
In the above described conventional method of manufacturing the semiconductor device, in view of the recent improvement in the device fabrication technology, circuit pattern is extremely complicated. In memory device of the most advanced ultra-LSI, contact step and patterning step are repeatedly carried out several times. Accordingly, in the later steps, unevenness becomes great on the semiconductor surface to cause problem that the adhesiveness of lead pattern material in the circuit pattern is impaired. Accordingly, in the memory device of most advanced large capacity, in order to eliminate unevenness of semiconductor substrate surface developed in later steps, introduction of leveling process is proposed, such that thickness of the insulating inter-layer film is increased twice or trice as much as in the conventional technology so as to level the surface. Consequently, as shown in FIG. 5 (c), in the lead patterning process, since the lead pattern material 36 composed of opaque film is disposed on the insulating inter-layer film having substantially smooth surface, alignment light irradiated from above the alignment mark 32 is reflected by the surface of lead pattern material 36. In the alignment method utilizing reflecting light or refracting light, when the unevenness due to the mark is relatively small on the surface around the alignment mark, since S/N of alignment signal defected from the alignment mark becomes weak, it is obvious to affect the alignment accuracy.
Further, conventionally in the method of marking the semiconductor device, method of forming measurement mark for measuring amount of alignment error is such that, firstly a film is formed over the semiconductor substrate, and thereafter a part of circuit pattern is formed by the film through lithography and etching process and concurrently reference or aligning pattern of the measurement mark for measuring the alignment error amount (such reference pattern is generally called male pattern, and therefore hereinafter referred to as male pattern) is formed on a margin portion of the circuit pattern. Then, after forming another film used in subsequent processing step over the entire surface of semiconductor substrate and coating photoresist, exposure is carried out by using exposure instrument. Then, mask pattern for etching is formed by developing process on the semiconductor substrate, and concurrently a remaining to-be-aligned pattern (generally called female pattern and therefore hereinafter referred to as female pattern) of the measurement mark is formed for measuring alignment error amount related to the exposure result on a margin portion of the circuit pattern.
In this conventional technology, the positioning must be carried out most accurately for a pattern having the least design margin among the previously formed circuit pattern. In view of this, the male pattern of measurement mark must be provisionally formed by a particular coating film having the most strict design margin. Accordingly, a plurality of processing steps may be interposed before forming the female pattern.
FIG. 6 is a plan view of mark for measuring alignment error amount by visual check through the conventionally used microscope (such mark is generally called vernier). The vernier is comprised of a male pattern 111 and a female pattern 112. By using pitch difference between the male and female patterns 111 and 112, the relative deviation amount (amount of scale of vernier) between the patterns is visually read to measure the alignment error amount.
FIG. 8 is production step chart taken along line A-A of FIG. 6 to show an example of the conventional manufacturing steps. In the step of forming gate electrode on the semiconductor substrate 103, the male pattern 111 is formed of gate electrode material (FIG. 8 (a)). Next, an optically transparent film 104 such as PSG (phosphorus siligate glass) film and SiO.sub.2 (silicon dioxide) film is formed as an insulating inter-layer film (drawing omitted). In order to carry out following lead patterning on the gate electrode, a process step is carried out to remove a part of the insulating inter-layer film 104 just above the gate electrode (such process step is generally called contact step). In general, in order to avoid short-circuit of lead pattern, it is not necessary to remove the insulating inter-layer film other than that corresponding to the gate electrode. Accordingly, a portion of the insulating inter-layer film 104 is left as it is on the male pattern 111. After the contact step, in order to proceed to subsequent patterning step, optically opaque lead material 106 such as aluminium is formed on the semiconductor substrate, and thereafter photoresist 105 is coated (FIG. 8 (b)). Next, after carrying out exposure by exposure instrument and developing process, female pattern 121 is formed. Generally, in view of the design margin, removal of the insulating inter-layer film and lead patterning must be carried out precisely to the given position on the gate electrode without causing short-circuit and open-circuit. Accordingly, the female pattern 121 shown in FIG. 8 (c) is formed relative to the male pattern of vernier provisionally formed from the gate electrode material so as to read the alignment error amount to carry out feedback compensation effective to reduce the alignment error during the exposure process in the patterning step to zero as close as possible.
FIG. 7 is a plan view of measurement mark used for measuring alignment error amount according to other conventional optical length-measurement method. This optical length-measurement method is such that laser beam light having a given wavelength and spot size is scanned in the direction of line B--B, and scattered light or positive reflected light from the male pattern 112 and female pattern 122 is detected by a given detection system so that the obtained signal is processed by computer to determine the distance between the pair of patterns. The distance between the pair of patterns is compared to predetermined design value, and the difference between the design value and the measured value is alignment error amount. FIG. 9 is a production step chart shown along B--B line of FIG. 7. The flow of production steps is similar to that of the conventional method explained in conjunction with FIG. 8.
In the above described conventional production method of semiconductor device, in view of the recent improvement of device production technology, the circuit pattern becomes considerably complicated. Therefore, in the most advanced large capacity memory product of ultra-LSI, the contact step and the patterning step are repeatedly carried out several times. Accordingly, in later steps, unevenness of the semiconductor substrate surface becomes greater, resulting in causing a problem that the adhesiveness of lead pattern material is impared in the circuit pattern.
Thus, in the most advanced large capacity memory products, in order to eliminate unevenness of the semiconductor surface developed in the later steps, a leveling process is proposed such that the thickness of an insulating inter-layer film is increased twice or trice as much as usual so as to level the surface. Accordingly, in the lead patterning step shown in FIG. 8 (c) and FIG. 9 (c), optically opaque lead pattern material is formed on the insulating inter-layer film 104 having an almost perfectly smooth surface.
Further, in both cases, the male pattern of alignment error amount measurement mark is formed under the smooth insulating inter-layer film. When undertaking a visual check from above the pattern by means of an optical microscope, it is impossible to recognize the step portion of male pattern, because the lead pattern material of upper layer is optically opaque and has the surface almost perfectly formed in the flat shape. With regard to the optical distance-measurement method, in a similar way, due to the flatness of surface, it is impossible to recognize the pattern, because the scattered light or positive reflecting light from the pattern edge with utilizing unevenness of the male pattern is very weak and the S/N ratio of the detected signal is also very weak. Accordingly, when applying the conventional method of producing a semiconductor device, there may be caused a drawback such that the measurement of the alignment error amount is impossible because the male pattern cannot be recognized.